-- $Id: $
-- File name:   RCV_FIFO.vhd
-- Created:     10/6/2010
-- Author:      Christopher Sakalis
-- Lab Section: 4
-- Version:     1.0  Initial Design Entry
-- Description: RCV_FIFO.


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY ECE337_IP;
USE ECE337_IP.ALL;

entity RCV_FIFO is
  port(
          CLK : in std_logic;
        RST_N : in std_logic;
     R_ENABLE : in std_logic;
     W_ENABLE : in std_logic;
       W_DATA : in std_logic_vector (7 downto 0);
       R_DATA : out std_logic_vector (7 downto 0);
        EMPTY : out std_logic;
         FULL : out std_logic);
end RCV_FIFO;


ARCHITECTURE structural OF RCV_FIFO IS

  --Declare components
  component Fifo
    port (
      RCLK, WCLK, RST_N : in std_logic;
      RENABLE, WENABLE  : in std_logic;
      WDATA             : in std_logic_vector(7 downto 0);
      RDATA             : out std_logic_vector(7 downto 0);
      EMPTY, FULL       : out std_logic);
  end component;

  --Declare signals?

   --signal RCV_W_temp: std_logic_vector(7 downto 0);


  --Link the components
begin


 FIFO_BLOCK: Fifo port map(
             WCLK => CLK,
             RCLK => CLK,
            RST_N => RST_N,
          RENABLE => R_ENABLE,
          WENABLE => W_ENABLE,
            WDATA => W_DATA,
            RDATA => R_DATA,
            EMPTY => EMPTY,
             FULL => FULL);

end structural;





